The present invention relates in general to memory devices, and in particular, to an interleaved memory readable in a synchronous mode or in a random access asynchronous mode with fast access times. The interleaved memory is readable in the synchronous mode by successive locations with a sequential type of access, commonly referred to as a burst mode.
In a standard memory a read cycle is defined from a request of data effected by the input of a new address, to the final output of the bits stored in the addressed location (byte, word, etc.). Internally, the reading process evolves through several steps. These steps start from the acquisition of the new address, to its decoding, to the generation of synchronizing pulses of the sensing circuits, and to the output of the read data.
The ATD (Address Transition Detection) signal recognizes a change of the address input by the external circuitry, and therefore, the new request of access and initiates a new read cycle. After enabling the sense amplifiers by the signal SAenable, an equalization of the sensing circuitry takes place. At the end of which, as timed by the signal EQZ, the effective reading of the memory cells takes place. Finally, after a certain interval of time that may vary from device to device, by way of a signal SAlatch, the recording of the read data into the latches in cascade to the sense amplifiers takes place, from where the read word may be transferred to the output buffers.
In memory devices designed for a synchronous read mode with a sequential type (burst) of access, the reading process exploits the fact that the reading takes place by successive locations. That is, the subsequent memory location to be read, and therefore, its address, is predictable from the address of the location being currently read.
A subgroup of these sequential (burst) synchronous read mode memories is represented by the interleaved memories. A burst access interleaved memory is described in U.S. Pat. No. 5,559,990, for example. In this type of memory, the cell array is divided in two semi-arrays or banks, each having its own read circuitry. The read streams of the two banks are thereafter superimposed according to one of the most commonly followed approaches, and are outphased (i.e., out of phase) from each other. While on one of the two banks or semi-array the steps of evaluation and transfer of the data to the output are being performed, on the other bank or semi-array (the next location to be addressed) a new read cycle may be started without waiting for the conclusion of the current read cycle that involves the first semi-array.
In interleaved memories, a basic scheme of which is depicted in FIG. 1, the array is divided into two independent banks or semi-arrays, EVEN and ODD, respectively, each having its own independent read path. Typically, there are two counters (one for each bank) containing the address of the currently pointed memory location. In case of simultaneous reading processes evolving respectively on the two semi-arrays, the least significant bit of the address (AO) supports the multiplexing between the EVEN and the ODD banks. If A0=0, the data coming from the EVEN semi-array will be made available at the output. If A0=1, the data coming from the ODD semi-array will be made available at the output.
As it is commonly known, the reading of the two semi-arrays is carried out according to one of two different approaches. A first approach is simultaneous readings and multiplexing of the outputs. A second approach involves time readings that are out of phase.
According to the first approach, the readings are simultaneous on the two banks. The data read are stored in respective output registers and made available to the outside world in synchronization with an external clock signal. According to the second approach, the readings on the two semi-arrays have an alternate and interleaved evolution over time.
The first approach, though offering a simpler hardware implementation, limits the minimization of the start times of synchronous read cycles. For a better comprehension, it is necessary to consider the basic steps that are performed when passing from an asynchronous read mode to a synchronous read mode. With reference to the scheme of FIG. 2, and starting the reading from an address X, the latter will be loaded on the EVEN bank counter and on the ODD bank counter, less the least significant bit (A0) of the address. The two counters will point to the same location X of the respective bank or semi-array.
If A0=0: the first read data is relative to the address X of the bank EVEN and the successive read data is the data a X of the bank ODD.
If A0=1: the first read data is relative to the address X of the bank ODD and the successively read data is relative to the X+1 address of the bank EVEN.
In the first case, it is sufficient to perform a simultaneous reading of the two banks and multiplex the outputs. In the second instance, it is necessary to increment the counter before starting the reading on the bank EVEN.
Usually, known synchronous memory devices do not make any initial increment and wait for the successive cycle for incrementing both counters, and therefore, read the location X+1 of the banks EVEN and ODD. This makes the times of the first read cycle and of the second sequential read cycle at best equal to the asynchronous read mode time of the memory.
In general, it may be stated that the efficient management of the read processes has a direct influence of the performance of the memory device. Many read-path architectures have been proposed. Known read-path architectures have generally been conceived for responding efficiently to either one or the other of the two modes of operation: asynchronous or synchronous.
If a memory device is designed to be read in asynchronous mode, it will be generally provided with a rather simple control circuitry for the read data streams. This allows the use of adaptive structures, such as dummy wordlines and dummy sense amplifiers, while leaving the reading circuitry free to evolve as fast as possible in order to achieve the shortest asynchronous access delays.
In contrast, in memory devices designed to function in a burst access mode or in a synchronous read mode, the possibility of making available in output a certain number of words read and stored in advance, permits, after a first asynchronous access, as long as it may be, a series of extremely fast read cycles. In this case though, the control logic must intervene extensively to manage the sense amplifiers which should not be left to evolve freely but be enabled, equalized and read at precise instants established by the control system. Prior European Patent Application Serial No. EP-98830801, filed on Dec. 30, 1998, and Italian Patent Application Serial No. MI99A00248, filed on Nov. 26, 1999, describe burst-mode EPROM devices with the above characteristics. These patent applications are both incorporated herein by reference in their entirety, and are assigned to the assignee of the present invention.
The access mode in a reading phase of operation is set to a specific protocol of use of two of the external protocol signals. These two signals are the address input latches enabling signal ALE and of the read stimulation signal RD.
The counters of the two semi-arrays, or the counter of the first bank and a more simpler register which functions as an address counter of the second bank, are incremented distinctly from one another. This is different from what is commonly done in interleaved memory devices. The readings are thus out of phase on the two banks from the first (asynchronous) read cycle. In this way, the memory device of the invention is perfectly able to switch to a synchronous mode reading phase at any time, which practically cuts in half the access time to such a mode.
The two different reading processes, according to an asynchronous random access mode and according to a synchronous burst access mode remain congruent with each other, having an alternate and interleaved evolution in time, as described in European Patent Application No. 00830068.3, filed on Jan. 31, 2000. This application is incorporated herein by reference in its entirety, and is assigned to the assignee of the present invention.
The reading of a standard memory is an asynchronous process that, starting from an initial stimulation generated by the switching of at least an external address line, evolves as far as to produce the new data to be output.
In view of the foregoing background, it is an object of the present invention to provide an improved interleaved data path and output management architecture for an interleaved memory that satisfies the particular control requirements that are imposed for reading an interleaved memory in an asynchronous random access mode or in a synchronous burst access mode.
The architecture of the invention is based on using three distinct registers. The first two of which are respectively dedicated to store the data read by respective arrays of sense amplifiers for two banks of memory cells of an interleaved memory. The third register receives as an input, under control of the timing circuitry of the memory, the data previously stored in one of the first two registers. The data passes through an array of pass-gates which are driven in common by a control signal generated by the timing circuitry. The data loaded in the third register is eventually transferred to the inputs of the output buffers, which are in turn controlled by external signals of the read protocol of the memory.
The structure employs three distinct registers for storing the data, which allows management in a relatively straightforward manner, operation of the memory device under all conditions contemplated by the protocol.
The use of three distinct registers permits readings on the two banks that are substantially uncorrelated among each other. The readings may in fact be out of phase or simultaneous depending on the starting stimulation and at the end of the read process. The sense amplifiers of each bank update a respective register coupled in cascade on the sense amplifier array of each bank.
According to a preferred embodiment of the invention, the control and timing circuit of the memory includes a special pulse generating circuit for generating signals for interleaved loading of data from the pair of registers in cascade of the two respective banks of sense amplifiers. These signals are generated into an output data register. A control circuit for the output buffers uses a peculiar locking mechanism that allows the duration of the load pulses for data in the output register to be advantageously extended, and the downloading of the data toward the output buffers.
These and other aspects will become even more evident through the following description of several preferred embodiments of the invention.